Patent Number: 8,819,612

Title: Analyzing timing requirements of a hierarchical integrated circuit design

Abstract: Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete.

Inventors: Helvey; Timothy D. (Rochester, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/26/12018