Patent Number: 8,819,690

Title: System for reducing data transfer latency to a global queue by generating bit mask to identify selected processing nodes/units in multi-node data processing system

Abstract: A system for efficient dispatch/completion of a work element within a multi-node data processing system. The system comprises a processor performing the functions of: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

Inventors: Alexander; Benjamin G. (Austin, TX), Bellows; Gregory H. (Austin, TX), Madruga; Joaquin (Austin, TX), Minor; Barry L. (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 9/46 (20060101)

Expiration Date: 8/26/12018