Patent Number: 8,822,137

Title: Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication

Abstract: An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

Inventors: Lin; Qinghuang (Yorktown Heights, NY), Mehta; Sanjay (Niskayuna, NY), Shobha; Hosadurga (Niskayuna, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 23/48 (20060101)

Expiration Date: 9/02/12018