Patent Number: 8,823,093

Title: High-voltage transistor structure with reduced gate capacitance

Abstract: In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

Inventors: Banerjee; Sujit (San Jose, CA), Parthasarathy; Vijay (Mountain View, CA)

Assignee: Power Integrations, Inc.

International Classification: H01L 29/76 (20060101)

Expiration Date: 9/02/12018