Patent Number: 8,871,586

Title: Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

Inventors: Scheiper; Thilo (Dresden, DE), Hoentschel; Jan (Dresden, DE), Lenski; Markus (Dresden, DE), Stephan; Rolf (Dresden, DE)


International Classification: H01L 21/8234 (20060101)

Expiration Date: 2018-10-28 0:00:00