Patent Number: 8,872,282

Title: Semiconductor device

Abstract: A semiconductor device is implementated that includes a source region, multiple elongated drain regions, a channel region, a source electrode, a drain electrode, and a gate electrode. The source region is a flat planar region formed on a compound semiconductor layer. The multiple elongated drain regions are formed so that they are each electrically isolated from each other on the compound semiconductor layer. The channel region is formed so that it contacts one side of the source region and is electrically isolated from the source region and the multiple elongated drain regions. The source electrode is formed at least in a portion on top of the source region. The drain electrode is formed so that it is connected electrically to the multiple elongated drain regions. The gate electrode is formed so that it is connected electrically to the multiple channel regions.

Inventors: Shim; Jeoungchill (Kanagawa-ken, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 27/088 (20060101); H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 27/085 (20060101); H01L 21/336 (20060101)

Expiration Date: 2018-10-28 0:00:00