Patent Number: 8,872,306

Title: Electrical interconnection structures including stress buffer layers

Abstract: Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

Inventors: Jin; Jeonggi (Osan-si, KR), Park; Jeong-woo (Suwon-si, KR), Choi; Ju-il (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 23/525 (20060101)

Expiration Date: 2018-10-28 0:00:00