Patent Number: 8,872,322

Title: Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Inventors: Gorman; Kevin W. (Fairfax, VT), Leu; Derek H. (Hopewell Junction, NY), Mondal; Krishnendu (Bangalore, IN), Sethuraman; Saravanan (Bangalore, IN)

Assignee: International Business Machines Corporation

International Classification: G01R 31/28 (20060101)

Expiration Date: 2018-10-28 0:00:00