Patent Number: 8,872,334

Title: Method for manufacturing semiconductor device

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Inventors: Yamamichi; Shintaro (Tokyo, JP), Kikuchi; Katsumi (Tokyo, JP), Nakashima; Yoshiki (Tokyo, JP), Mori; Kentaro (Tokyo, JP)

Assignee: NEC Corporation

International Classification: H01L 23/48 (20060101)

Expiration Date: 2018-10-28 0:00:00