Patent Number: 8,878,237

Title: Active edge structures providing uniform current flow in insulated gate turn-off thyristors

Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n- layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n- epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.

Inventors: Akiyama; Hidenori (Miyagi Sendai, JP), Blanchard; Richard A. (Los Altos, CA), Tworzydlo; Woytek (Austin, TX)

Assignee: Pakal Technologies LLC

International Classification: H01L 29/66 (20060101)

Expiration Date: 2019-11-04 0:00:00