Patent Number: 8,878,510

Title: Reducing power consumption in a voltage regulator

Abstract: A voltage regulator includes an amplifier, a first buffer and a second buffer. The amplifier is designed to generate an error voltage between a reference voltage and a voltage at an output node of the voltage regulator. The first buffer is coupled to receive the amplified error voltage and, in response, to drive a first pass transistor. The first buffer includes a non-linear resistance element. The resistance of the non-linear resistance element varies non-linearly with a load current drawn from the output node. The second buffer is coupled to receive the amplified error voltage, and in response, to drive a second pass transistor. The second buffer includes a linear resistance element. The resistance of the linear element is a constant. The use of the non-linear resistance element enables reduction in power consumption in the voltage regulator.

Inventors: Bhattacharyya; Prasun Kali (Bangalore, IN), Easwaran; Prakash (Bangalore, IN)

Assignee: Cadence AMS Design India Private Limited

International Classification: G05F 3/08 (20060101)

Expiration Date: 2019-11-04 0:00:00