Patent Number: 8,879,346

Title: Mechanisms for enabling power management of embedded dynamic random access memory on a semiconductor integrated circuit package

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Inventors: Kam; Timothy Y. (Portland, OR), Schwartz; Jay D. (Aloha, OR), Kim; Seongwoo (Beaverton, OR), Gunther; Stephen H. (Beaverton, OR)

Assignee: Intel Corporation

International Classification: G11C 5/14 (20060101)

Expiration Date: 2019-11-04 0:00:00