Patent Number: 8,879,611

Title: Fully-digital BIST for RF receivers

Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

Inventors: Dhayni; Achraf (Vallauris, FR), Kuenen; Jeroen (Beuningen, NL)

Assignee: ST-Ericsson SA

International Classification: H04B 17/00 (20060101)

Expiration Date: 2019-11-04 0:00:00