Patent Number: 8,880,382

Title: Analyzing a patterning process using a model of yield

Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

Inventors: Bagheri; Saeed (Croton on Hudson, NY), Heng; Fook-Luen (Yorktown Heights, NY), Joshi; Rajiv Vasant (Yorktown Heights, NY), Lai; Kafai (Poughkeepsie, NY), Melville; David Osmond (New York, NY), Mukhopadhyay; Saibal (Atlanta, GA), Rosenbluth; Alan E (Yorktown Heights, NY), Singh; Rama N. (Bethel, CT), Tian; Kehan (Poughkeepsie, NY)

Assignee: International Business Machines Corporation

International Classification: G06G 7/48 (20060101)

Expiration Date: 2019-11-04 0:00:00