Patent Number: 8,880,779

Title: Debugging a memory subsystem

Abstract: In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.

Inventors: Fai; Anthony (Palo Alto, CA), Wakrat; Nir Jacob (Los Altos, CA), Seroff; Nicholas (Los Gatos, CA)

Assignee: Apple Inc.

International Classification: G06F 12/02 (20060101)

Expiration Date: 2019-11-04 0:00:00