Patent Number: 8,880,860

Title: Methods and apparatus for saving conditions prior to a reset for post reset evaluation

Abstract: A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.

Inventors: Sartorius; Thomas Andrew (Raleigh, NC), Singh; Subodh (Bangalore, IN)

Assignee: QUALCOMM Incorporated

International Classification: G06F 15/177 (20060101)

Expiration Date: 2019-11-04 0:00:00