Patent Number: 8,881,083

Title: Methods for improving double patterning route efficiency

Abstract: A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Inventors: Deng; Yunfei (Sunnyvale, CA), Yuan; Lei (Cupertino, CA), Yoshida; Hidekazu (San Jose, CA), Kim; Juhan (Santa Clara, CA), Rashed; Mahbub (Cupertino, CA), Kye; Jongwook (Pleasanton, CA)

Assignee: GLOBALFOUNDRIES Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-11-04 0:00:00