Patent Number: 8,881,087

Title: Power routing with integrated decoupling capacitance

Abstract: An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network (200) which comprises, in a first one (metalz) of the conduction layers, a first mesh structure (210) of electrically conductive material for distribution of a first electrical potential (POWER) of the power supply. The power-supply distribution network also comprises, in a second one (metalz+1) of the conduction layers, different from the first one of the conduction layers, a second mesh structure (220) of electrically conductive material for distribution of a second electrical potential (GROUND) of the power supply. In the first one (metalz) of the conduction layers, a first plurality of islands (212) of electrically conductive material is provided, each island being located in a hole (214) of the first mesh structure (210) and being electrically insulated from the first mesh structure with a dielectric material.

Inventors: Herder; Sjoerd (Den Hoorn, NL), Koning; Harro (Arnhem, NL)

Assignee: ST-Ericsson SA

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-11-04 0:00:00