Patent Number: 8,881,089

Title: Physical synthesis optimization with fast metric check

Abstract: A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions ("selected solution") for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.

Inventors: Alpert; Charles Jay (Austin, TX), Bee; Glenn R. (Elgin, TX), Li; Zhuo (Cedar Park, TX), Mahmud; Tuhin (Austin, TX), Quay; Stephen T. (Austin, TX), Reddy; Lakshmi N. (Briarcliff Manor, NY), Sze; Chin Ngai (Austin, TX), Wei; Yaoguang (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-11-04 0:00:00