Patent Number: 9,385,078

Title: Self aligned via in integrated circuit

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Inventors: Feurprier; Yannick (Watervliet, NY), Lee; Joe (Albany, NY), Liebmann; Lars W. (Poughquag, NY), Mignot; Yann (Slingerlands, NY), Spooner; Terry A. (Clifton Park, NY), Trickett; Douglas M. (Altamont, NY), Yilmaz; Mehmet (Ankara, TR)

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification: H01L 23/522 (20060101); H01L 21/768 (20060101)

Expiration Date: 2020-07-05 0:00:00