Patent Number: 9,385,189

Title: Fin liner integration under aggressive pitch

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Inventors: Sung; Min Gyu (Latham, NY), Tripathi; Neeraj (Albany, NY)


International Classification: H01L 21/02 (20060101); H01L 21/8238 (20060101); H01L 29/161 (20060101); H01L 29/16 (20060101); H01L 27/092 (20060101); H01L 29/66 (20060101); H01L 21/311 (20060101); H01L 29/06 (20060101)

Expiration Date: 2020-07-05 0:00:00