Patent Number: 9,431,321

Title: Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.

Inventors: Watanabe; Shinya (Oita, JP), Higashi; Kazuyuki (Oita, JP), Kamoto; Taku (Oita, JP)

Assignee: KABUSHIKI KAISHA TOSHIBA

International Classification: H01L 23/544 (20060101); H01L 21/683 (20060101); H01L 21/66 (20060101); H01L 23/48 (20060101); H01L 21/82 (20060101); H01L 23/538 (20060101); H01L 21/768 (20060101); H01L 23/00 (20060101)

Expiration Date: 2020-08-30 0:00:00