Patent Number: 9,741,707

Title: Immunity to inline charging damage in circuit designs

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Inventors: Henderson; Zachary (Jamaica Plain, MA), Hibbeler; Jason D. (Williston, VT), Hook; Terence B. (Jericho, VT), Palmer; Nicholas (Beaverton, OR), Peterson; Kirk D. (Jericho, VT)


International Classification: H01L 27/02 (20060101); G06F 17/50 (20060101); H01L 29/06 (20060101)

Expiration Date: 2021-08-22 0:00:00