Patent Number: 9,741,769

Title: Vertical memory structure with array interconnects and method for producing the same

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Inventors: Franca-Neto; Luiz M. (Sunnyvale, CA), Lille; Jeffrey (Sunnyvale, CA)

Assignee: Western Digital Technologies, Inc.

International Classification: H01L 27/00 (20060101); H01L 45/00 (20060101); H01L 27/11578 (20170101); H01L 27/11551 (20170101); H01L 27/06 (20060101); G11C 13/00 (20060101); H01L 27/24 (20060101)

Expiration Date: 2021-08-22 0:00:00