Patent Number: RE37,500

Title: System for partitioning and testing submodule circuits of an integrated circuit

Abstract: A system for providing testing capability of individual submodules on an integrated circuit module. A test bus having a plurality of conductors is connected to selected internal ports of said submodules through three-way analog switches. Each three-way analog switch provides the capability to observe and control an internal port through combination of the ON/OFF status of two transmission gates. Test patterns for controlling the transmission gates may be provided by onboard D flip-flops which are externally programmed to control or observe ports of an individual submodule.

Inventors: Lee; Nai-Chi (Peekskill, NY)

Assignee: North American Philips Corporation

International Classification: G01R 31/3185 (20060101); G01R 31/28 (20060101); G01R 031/28 ()

Expiration Date: 01/08/2019